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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7376* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 * patent number: 5495245 6 15 v operation digital potentiometer functional block diagram gnd v dd sdo ad7376 7-bit serial register q d ck 7 7-bit latch r 7 sdi clk a w b v ss shdn cs rs shdn features 128 position potentiometer replacement 10 k v , 50 k v , 100 k v , 1 m v power shutdown: less than 1 m a 3-wire spi compatible serial data input +5 v to +30 v single supply operation 6 5 v to 6 15 v dual supply operation midscale preset applications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion programmable filters, delays, time constants line impedance matching power supply adjustment general description the ad7376 provides a single channel, 128-position digitally- controlled variable resistor (vr) device. this device performs the same electronic adjustment function as a potentiometer or vari- able resistor. these products were optimized for instrument and test equipment applications where a combination of high voltage with a choice between bandwidth or power dissipation are avail- able as a result of the wide selection of end-to-end terminal resis- tance values. the ad7376 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the spi-compatible serial-input regis- ter. the resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code trans- ferred into the vr latch. the variable resistor offers a completely programmable value of resistance between the a terminal and the wiper or the b terminal and the wiper. the fixed a to b terminal resistance of 10 k w , 50 k w , 100 k w or 1 m w has a nominal tem- perature coefficient of C300 ppm/ c. the vr has its own vr latch which holds its programmed resis- tance value. the vr latch is updated from an internal serial-to- parallel shift register which is loaded from a standard 3-wire serial-input digital interface. seven data bits make up the data word clocked into the serial data input register (sdi). only the last seven bits of the data word loaded are transferred into the 7-bit vr latch when the cs strobe is returned to logic high. a serial data output pin (sdo) at the opposite end of the serial register allows simple daisy-chaining in multiple vr applications without additional external decoding logic. the reset ( rs ) pin forces the wiper to the midscale position by loading 40 h into the vr latch. the shdn pin forces the resistor to an end-to-end open circuit condition on the a terminal and shorts the wiper to the b terminal, achieving a microwatt power shutdown state. when shutdown is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown as long as power to v dd is not re- moved. the digital interface is still active in shutdown so that code changes can be made that will produce a new wiper posi- tion when the device is taken out of shutdown. the ad7376 is available in both surface mount (sol-16) and the 14-lead plastic dip package. for ultracompact solutions selected models are available in the thin tssop package. all parts are guaranteed to operate over the extended industrial temperature range of C40 c to +85 c. for operation at lower supply voltages (+3 v to +5 v), see the ad8400/ad8402/ ad8403 products. 6 1 lsb error band 6 1 lsb sdi (data in) sdo (data out) clk cs v dd v out 0v 0 1 0 1 0 1 0 1 d x d x t pd_max d' x d' x t ds t dh t ch t csh0 t css t cl t cs1 t csw t s t csh figure 1. detail timing diagram the last seven data bits clocked into the serial input register will be transferred to the vr 7-bit latch when cs returns to logic high. extra data bits are ignored.
C2C rev. 0 ad7376Cspecifications (v dd /v ss = 6 15 v 6 10% or 6 5 v 6 10%, v a = +v dd , v b = v ss /0 v, C40 8 c < t a < +85 8 c unless otherwise noted.) electrical characteristics parameter symbol conditions min typ 1 max units dc characteristics rheostat mode (specifications apply to all vrs) resistor differential nl 2 r-dnl r wb , v a = nc C1 0.25 +1 lsb resistor nonlinearity 2 r-inl r wb , v a = nc C1 0.5 +1 lsb nominal resistor tolerance d rt a = +25 c C30 30 % resistance temperature coefficient r ab / d tv ab = v dd , wiper = no connect C300 ppm/ c wiper resistance r w i w = 15 v/r nominal 120 200 w wiper resistance r w i w = 5 v/r nominal 200 w dc characteristics potentiometer divider mode (specifications apply to all vrs) resolution n 7 bits integral nonlinearity 3 inl C1 0.5 +1 lsb differential nonlinearity 3 dnl C1 0.1 +1 lsb voltage divider temperature coefficient d v w / d t code = 40 h 5 ppm/ c full-scale error v wfse code = 7f h C2 C0.5 +0 lsb zero-scale error v wzse code = 00 h 0 +0.5 +1 lsb resistor terminals voltage range 4 v a, b, w v ss v dd v capacitance 5 a, b c a, b f = 1 mhz, measured to gnd, code = 40 h 45 pf capacitance 5 wc w f = 1 mhz, measured to gnd, code = 40 h 60 pf shutdown supply current 6 i a_sd v a = v dd , v b = 0 v, shdn = 0 0.01 1 m a shutdown wiper resistance r w_sd v a = v dd , v b = 0 v, shdn = 0, v dd = +15 v 170 400 w common-mode leakage i cm v a = v b = v w 1na digital inputs and outputs input logic high v ih v dd = +5 v or +15 v 2.4 v input logic low v il v dd = +5 v or +15 v 0.8 v output logic high v oh r l = 2.2 k w to +5 v 4.9 v output logic low 7 v ol i ol = 1.6 ma, v logic = +5 v, v dd = +15 v 0.4 v input current i il v in = 0 v or +15 v 1 m a input capacitance 5 c il 5pf power supplies power supply range v dd /v ss dual supply range 4.5 16.5 v power supply range v dd single supply range, v ss = 0 4.5 28 v supply current i dd v ih = +5 v or v il = 0 v, v dd = +5 v 0.0001 0.01 ma supply current i dd v ih = +5 v or v il = 0 v, v dd = +15 v 0.75 2 ma supply current i ss v ih = +5 v or v il = 0 v, v ss = C5 v or C15 v 0.02 0.1 ma power dissipation 8 p diss v ih = +5 v or v il = 0 v, v dd = +15 v, v ss = C15 v 11 30 mw power supply sensitivity pss d v dd = +5 v 10%, or d v ss = C5 v 10% 0.05 0.15 %/% pss d v dd = +15 v 10% or d v ss = C15 v 10% 0.01 0.02 %/% dynamic characteristics 5, 9, 10 bandwidth C3 db bw_10k r ab = 10 k w , code = 40 h 520 khz bandwidth C3 db bw_50k r ab = 50 k w , code = 40 h 125 khz bandwidth C3 db bw_100k r ab = 100 k w , code = 40 h 60 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.005 % v w settling time t s v a = 10 v, v b = 0 v, 1 lsb error band 4 m s resistor noise voltage e n_wb r wb = 25 k w , f = 1 khz, rs = 0 14 nv ? hz interface timing characteristics (applies to all parts [notes 5, 11]) input clock pulsewidth t ch , t cl clock level high or low 120 ns data setup time t ds 30 ns data hold time t dh 20 ns clk to sdo propagation delay 12 t pd r l = 2.2 k w , c l < 20 pf 10 100 ns cs setup time t css 120 ns cs high pulsewidth t csw 150 ns reset pulsewidth t rs 120 ns clk rise to cs rise hold time t csh 120 ns cs rise to clock rise setup t cs1 120 ns
C3C rev. 0 ad7376 ordering guide temperature package package model k v range description options ad7376an10 10 C40 c to +85 c pdip-14 n-14 ad7376ar10 10 C40 c to +85 c sol-16 r-16 ad7376aru10 10 C40 c to +85 c tssop-14 ru-14 ad7376an50 50 C40 c to +85 c pdip-14 n-14 ad7376ar50 50 C40 c to +85 c sol-16 r-16 AD7376ARU50 50 C40 c to +85 c tssop-14 ru-14 ad7376an100 100 C40 c to +85 c pdip-14 n-14 ad7376ar100 100 C40 c to +85 c sol-16 r-16 ad7376aru100 100 C40 c to +85 c tssop-14 ru-14 ad7376an1m 1,000 C40 c to +85 c pdip-14 n-14 ad7376ar1m 1,000 C40 c to +85 c sol-16 r-16 ad7376aru1m 1,000 C40 c to +85 c tssop-14 ru-14 die size: 101.6 mil 127.6 mil, 2.58 mm 3.24 mm number transistors: 840 notes 1 1 typicals represent average readings at +25 c, v dd = +15 v, and v ss = C15 v. 1 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. see figure 27. test circuit. 1 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. see figure 26. test circuit. 1 4 resistor terminals a, b, w have no limitations on polarity with respect to each other. 1 5 guaranteed by design and not subject to production test. 1 6 measured at the a terminal. a terminal is open circuit in shutdown mode. 1 7 i ol = 200 m a for the 50 k w version operating at v dd = +5 v. 1 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 1 9 bandwidth, noise and settling time are dependent on the terminal resistance value chosen. the lowest r value results in the fas test settling time and highest band- width. the highest r value results in the minimum overall power consumption. 10 all dynamic characteristics use v dd = +15 v and v ss = C15 v. 11 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 1 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. switching characteristics are measured using both v dd = +5 v or +15 v. 12 propagation delay depends on value of v dd , r l and c l see applications section. specifications subject to change without notice. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7376 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings (t a = +25 c, unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +30 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v, C16.5 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +44 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd a x C b x , a x C w x , b x C w x . . . . . . . . . . . . . . . . . . . 20 ma digital input voltages to gnd . . . . . . . . . . 0 v, v dd + 0.3 v digital output voltage to gnd . . . . . . . . . . . . . . 0 v, +30 v operating temperature range . . . . . . . . . . . C40 c to +85 c maximum junction temperature (t j max) . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c package power dissipation . . . . . . . . . . . . (t j max C t a )/ q ja thermal resistance q ja p-dip (n-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 c/w soic (sol-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120 c/w tssop-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 c/w pin configurations pdip & tssop-14 sol-16 14 13 12 11 10 9 8 1 2 3 4 7 6 5 top view (not to scale) nc = no connect ad7376 w nc v dd sdo shdn sdi nc a b v ss gnd cs rs clk 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad7376 nc = no connect w nc v dd sdo sdi nc nc a b v ss gnd clk nc shdn cs rs
ad7376 C4C rev. 0 percent of nominal end-to-end resistance C % r ab 100 75 0 0 32 128 64 96 50 25 r wb r wa code C decimal figure 2. wiper to end terminal percent resistance vs. code temperature C 8 c nominal end-to-end resistance C k v 50 C55 C35 105 C15 5 25 45 65 85 49 47 46 45 48 v dd = +15v v ss = C15v r ab = 50k v nominal 125 figure 5. nominal resistance vs. temperature supply voltage (v dd - v ss ) C volts inl C lsb 1.0 51015202530 0.8 0.2 0 0.6 0.4 v a = 2.5v v b = 0v code = 40 h r ab = 50k v figure 8. potentiometer divider nonlinearity error vs. supply voltage Ctypical performance characteristics code C decimal r-inl error C lsb 0.5 C0.5 0 16 128 32 48 64 80 96 112 0.4 0.1 0 C0.2 C0.4 0.3 0.2 C0.1 C0.3 t a = C55 8 c t a = +25 8 c t a = +85 8 c v dd = +15v v ss = C15v v a = 2.5v v b = 0v r ab = 50k v figure 3. resistance step position nonlinearity error vs. code i wa C ma v wa C v 10 0 0.25 2 0.5 0.75 1 1.25 1.5 1.75 8 4 2 0 6 t a = +25 8 c v dd = +15v v ss = C15v r ab = 50k v 12 14 20 h 01 h 10 h 40 h 7f h code = 70 h figure 6. resistance linearity vs. conduction current code C decimal d v wb / d t potentiometer mode tempco C ppm/ 8 c 20 0 16 128 32 48 64 80 96 112 10 0 C5 5 v dd = +15v v ss = C15v v a = +2.5v v b = 0v C55 8 c < t a < +85 8 c r ab = 50k v 15 C10 C15 C20 C25 C30 figure 9. d v wb / d t potentiometer mode tempco code C decimal r-dnl error C lsb 0.25 C0.25 0 16 128 32 48 64 80 96 112 0.20 0.05 0 C0.10 C0.20 0.15 0.10 C0.05 C0.15 t a = C55 8 c t a = +25 8 c v dd = +15v v ss = C15v r ab = 50k v t a = +85 8 c figure 4. relative resistance step change from ideal vs. code supply voltage (v dd - v ss ) C volts r_inl C lsb 1.5 51015202530 1.2 0.3 0 0.9 0.6 i w = 100 m a, t a = +25 8 c data = 40 h figure 7. resistance nonlinearity error vs. supply voltage temperature C 8 c wiper contact resistance C v 1000 0 C55 C35 125 C15 5 25 45 65 105 900 600 500 300 100 800 700 400 200 v dd = +5v v ss = 0v 85 v dd = +5v v ss = C5v r ab = 50k v v dd = +15v v ss = C15v figure 10. wiper contact resistance vs. temperature
ad7376 C5C rev. 0 code C decimal inl nonlinearity error C lsb 0.25 C0.25 0 16 128 32 48 64 80 96 112 0.20 0.05 0 C0.10 C0.20 0.15 0.10 C0.05 C0.15 t a = C55 8 c t a = +25 8 c v dd = +15v v ss = C15v v a = +2.5v v b = 0v r ab = 50k v t a = +85 8 c figure 11. potentiometer divider nonlinearity error vs. code frequency C hz gain C db 1k C18 C24 C36 C48 C6 C12 C30 C42 a w op275 b v ss = C15v v ampl = 50mvrms v dd = +15v code = 7f h code = 40 h code = 20 h code = 10 h code = 08 h code = 04 h code = 02 h code = 01 h code = 00 h 0 10k 100k 1m r ab = 10k v figure 14. 10 k w gain vs. frequency vs. code frequency C hz gain C db 1k 10k 1m 100k 0 C54 C6 C12 C18 C24 C30 C36 C42 C48 b a op275 01 h 02 h 04 h 08 h 10 h 20 h code = 40 h code = 7f h 128khz amp = 50mv v dd = +15v v ss = C15v r l = 1m v r ab = 50k v figure 17. 50 k w gain vs. frequency vs. code code C decimal dnl C lsb 0.25 C0.25 0 16 128 32 48 64 80 96 112 0.20 0.05 0 C0.10 C0.20 0.15 0.10 C0.05 C0.15 v dd = +15v v ss = C15v v a = +2.5v v b = 0v r ab = 50k v figure 12. potentiometer divider differential nonlinearity error vs. code frequency C hz gain C db 100 C18 C24 C36 C48 C6 C12 C30 C42 a b w op275 v ss = C15v v ampl = 50mvrms v dd = +15v code = 7f h code = 40 h code = 20 h code = 10 h code = 08 h code = 04 h code = 02 h code = 01 h 0 1k 10k r ab = 1m v 100k r ab = 1m v figure 15. 1 m w gain vs. frequency vs. code 0 5 12 0 27.08 m s a2 1.6 v dly 5v 5v h o 2 m s b l w v dd = +15v v ss = C15v 2 m s/div code = 3f h v a = 12v v b = 0v f = 1 mhz figure 18. large signal settling time code C decimal rheostat mode tempco C ppm/ 8 c 40 C10 0 16 128 32 48 64 80 96 112 35 20 15 5 C5 30 25 10 0 v dd = +15v v ss = C15v r ab = 50k v figure 13. d r wb / d t rheostat mode tempco 259.8 m s 50m h o 5 m s b l w v dd = +15v v ss = e15v 5 m s/div code = 3f h 40 h 3f h v a = 2.5v v b = 0v f = 100 khz figure 16. midscale transition glitch frequency C hz 10 1.0 100 1k 10k 200k 0.001 0.010 0.0005 0.1 v dd = +15v v ss = C15v v a = 6 10v pCp code = 40 h r ab = 50k v thd C % non-inverting mode test ckt fig 35 non-inverting mode test ckt fig 36 figure 19. total harmonic distortion plus noise vs. frequency
ad7376 C6C rev. 0 frequency C hz gain C db C18 C24 C36 C48 C6 C12 C30 C42 a b w op275 v ss = C15v v ampl = 50mvrms v dd = +15v 0 1k 100k r ab = 100k v 1m 10k code = 7f h 40h 20h 10h 08h 04h 02h 01h figure 20. 100 k w gain vs. frequency vs. code v dd = +15v v ss = C15v v ampl = 50mvrms code = 40 h frequency C hz gain C db 0 C0.4 C0.8 C0.2 C0.6 10 100k 1m 10k 50k v 100k v 1m v a b w op275 C0.1 C0.7 C0.5 C0.3 0.1 C0.9 100 1k r ab = 10k v figure 23. gain flatness vs fre- quency vs. nominal resistance r ab temperature C 8 c C55 1.0 C35 C15 5 25 0.001 0.010 0.1 45 65 85 105 125 supply current C ma i ss @v ss = C15v, v logic = +15v i dd @v dd = +5v, v logic = +0.8v i dd @v dd = +5v, v logic = +5v i dd @v dd = +15v, v logic = 0v i dd @v dd = +15v, v logic = +5v r ab = 50k v 10 figure 26. supply current (i dd , i ss ) vs. temperature v dd = +15v v ss = C15v v ampl = 50mvrms code = 40 h frequency C hz gain C db C18 C24 C36 C48 C6 C12 C30 C42 0 1k 100k 1m 10k 50k v 100k v r ab = 1m v C54 10k v a b w op275 figure 21. C3 db bandwidth vs. nominal resistance +psrr v dd = +15v 6 10% v ss = C15v Cpsrr v dd = +15v v ss = C15v 6 10% +psrr v dd = +5v 6 10% v ss = C5v Cpsrr v dd = +5v v ss = C5v 6 10% frequency C hz psrr C db 10 100 1k 10k 100k 90 80 10 70 60 50 40 30 20 figure 24. power supply rejection vs. frequency temperature C 8 c C55 1.0 C35 C15 5 25 0.001 0.010 0.1 v dd = +15v v ss = C15v 45 65 85 105 125 shutdown current C m a figure 27. i a_sd shutdown current vs. temperature 235.2
ad7376 C7C rev. 0 parametric test circuits a w b v ms dut v+ = v dd 1lsb = v+/128 v+ figure 31. potentiometer divider nonlinearity error test circuit (inl, dnl) no connect i w a w b v ms dut figure 32. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) r w = v+ v dd v w2 - (v w1 + i w [r aw || r bw ]) and v w2 = v ms when i w = 1/r i w where v w1 = v ms when i w = 0 i ms v w i w = 1v/r nominal a w b dut v+ v ms figure 33. wiper resistance test circuit pss (%/%) = d v ms % d v+% psrr (db) = 20log d v ms d v+ ( ( v+ = v dd 6 10% or v ss 6 10% v dd a w b v ms v+ v a figure 34. power supply sensitivity test circuit (pss, psrr) dut a w b v in +18v v out C18v op275 figure 35. inverting programmable gain test circuit a b C18v dut w v in +18v v out op275 figure 36. noninverting programmable gain test circuit a b C18v dut w v in +18v v out op275 figure 37. gain vs. frequency test circuit supply voltage (v dd ) C volts input logic threshold voltage C volts 3.5 51015202530 3.0 1.0 0 2.5 2.0 v a = +5v v b = 0v v ss = 0v 0.5 1.5 figure 29. input logic threshold voltage vs. v dd supply voltage v dd = +15v v ss = C15v v dd = +5v v ss = 0v or C5v v logic i dd C m a 51015 800 0 1600 400 1200 0 figure 30. supply current (i dd ) vs. logic voltage
ad7376 C8C rev. 0 0.1v code = oo h i sw v ss to v dd w b dut 0.1v i sw r sw = figure 38. incremental on resistance test circuit i cm v cm w b dut v dd v ss nc a nc gnd figure 39. common-mode leakage current test circuit operation the ad7376 provides a 128-position digitally-controlled vari- able resistor (vr) device. changing the programmed vr set- tings is accomplished by clocking in a 7-bit serial data word into the sdi (serial data input) pin, while cs is active low. when cs returns high the last seven bits are transferred into the rdac latch setting the new wiper position. the exact timing require- ments are shown in figure 1. the ad7376 resets to a midscale by asserting the rs pin, sim- plifying initial conditions at power-up. both parts have a power shutdown shdn pin which places the rdac in a zero power consumption state where terminal a is open circuited and the wiper w is connected to b, resulting in only leakage currents being consumed in the vr structure. in shutdown mode the vr latch settings are maintained so that, returning to opera- tional mode from power shutdown, the vr settings return to their previous resistance values. d6 d5 d4 d3 d2 d1 d0 rdac latch & decoder r s r s r s r s shdn a w b r s = r nominal /128 figure 40. ad7376 equivalent rdac circuit programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a and b are available with values of 10 k w , 50 k w , 100 k w and 1 m w . the final three characters of the part number determine the nominal resistance value, e.g., 10 k w = 10; 50 k w = 50; 100 k w = 100; 1 m w = 1m. the nominal resistance (r ab ) of the vr has 128 contact points accessed by the wiper terminal, plus the b terminal contact. the 7-bit data word in the rdac latch is decoded to select one of the 128 possible settings. the wipers first connection starts at the b terminal for data 00 h . this bCtermi- nal connection has a wiper contact resistance of 120 w . the second connection (10 k w part) is the first tap point located at 198 w (= r ba [nominal resistance]/128 + r w = 78 w + 120 w ) for data 01 h . the third connection is the next tap point repre- senting 156 + 120 = 276 w for data 02 h . each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10041 w . the wiper does not directly con- nect to the b terminal. see figure 40 for a simplified diagram of the equivalent rdac circuit. the general transfer equation that determines the digitally pro- grammed output resistance between w and b is: r wb (d) = (d)/128 r ba + r w (1) where d is the data contained in the 7-bit vr latch, and r ba is the nominal end-to-end resistance. for example, when v b = 0 v and aCterminal is open circuit, the following output resistance values will be set for the following vr latch codes (applies to the 10 k w potentiometer). table i. dr wb (dec) ( v ) output state 127 10041 full-scale 64 5120 midscale ( rs = 0 condition) 1 276 1 lsb 0 198 zero-scale (wiper contact resistance) note that in the zero-s cale co ndition a finite wiper resistance of 120 w is pres ent. care should be taken to limit the current flow between w and b in this state to a maximum value of 5 ma to avoid degradation or possible destruction of the internal switch contact. like the mechanical potentiometer the rdac replaces, it is totally symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled resistance r wa . when these terminals are used the bCterminal should be tied to the wiper. setting the resistance value for r wa starts at a maxi- mum value of resistance and decreases as the data loaded in the latch is increased in value. the general transfer equation for this operation is: r wa ( d ) = (128- d )/128 r ba + r w (2) where d is the data contained in the 7-bit rdac latch, and r ba is the nominal end-to-end resistance. for example, when v a = 0 v and bCterminal is tied to the wiper w the following output resistance values will be set for the following rdac latch codes.
ad7376 C9C rev. 0 table ii. dr wa (dec) ( v ) output state 127 74 full-scale 64 5035 midscale ( rs = 0 condition) 1 9996 1 lsb 0 10035 zero-scale the typical distribution of r ba from device to device matching is process lot dependent having a 30% variation. the change in rba with temperature has a C300 ppm/ c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. for example connecting aCterminal to +5 v and bCterminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 lsb less than +5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 128-position resolution of the potentiometer divider. the general equation defining the output voltage with respect to ground for any given input voltage applied to termi- nals ab is: v w ( d ) = d /128 v ab + v b operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resis- tors, not the absolute value; therefore, the drift improves to 5 ppm/ c. gnd v dd sdo ad7376 7-bit serial register q d ck 7 r 7 sdi clk a w b v ss shdn cs rs shdn 7-bit rdac latch figure 41. block diagram digital interfacing the ad7376 contains a standard three-wire serial input control interface. the three inputs are clock (clk), cs and serial data input (sdi). the positive-edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation they should be de- bounced by a flip-flop or other suitable means. when cs is taken active low the clock loads data into the serial register on each positive clock edge, see table iii. the last seven bits clocked into the serial register will be transferred to the 7-bit rdac latch, see figure 41. extra data bits are ignored. the serial-data-output (sdo) pin contains an open drain n-channel fet. this output requires a pull-up resistor in order to transfer data to the next packages sdi pin. this allows for daisy chain- ing several rdacs from a single processor serial data line. clock period needs to be increased when using a pull-up resistor to the sdi pin of the following device in the series. capacitive loading at the daisy chain node sdo-sdi between devices must be accounted for to successfully transfer data. when daisy chaining is used, the cs should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the data bits are in the proper decoding location. this would require 14 bits of data when two ad7376 rdacs are daisy chained. during shutdown ( shdn ) the sdo output pin is forced to the off (logic high state) to disable power dissi- pation in the pull up resistor. see figure 42 for equivalent sdo output circuit schematic. table iii. input logic control truth table clk cs rs shdn register activity l l h h enables sr, enables sdo pin. p l h h shifts one bit in from the sdi pin. the seventh previously entered bit is shifted out of the sdo pin. x p h h loads sr data into 7-bit rdac latch. x h h h no operation. x x l h sets 7-bit rdac latch to mid- scale, wiper centered, and sdo latch cleared. x h p h latches 7-bit rdac latch to 40 h . x h h l opens circuits resistor aCterminal, connects w to b, turns off sdo output transistor. note p = positive edge, x = dont care, sr = shift register.
ad7376 C10C rev. 0 the data setup and data hold times in the specification table determine the data valid time requirements. the last seven bits of the data word entered into the serial register are held when cs returns high. at the same time cs goes high it transfers the 7-bit data to the vr latch. shdn sdi clk ck d q rs cs serial register rs sdo figure 42. detail sdo output schematic of the ad7376 all digital inputs are protected with a series input resistor and parallel zener esd structure shown in figure 43. applies to digital input pins cs , sdi, sdo, rs , shdn , clk 100 v v dd logic figure 43. equivalent esd protection circuit v ss a,b,w v dd figure 44. equivalent esd protection analog pins
ad7376 C11C rev. 0 14-lead plastic dip (n-14) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 14-lead tssop (ru-14) 14 8 7 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm). 16-lead wide body soic (r-16) 16 9 8 1 0.4133 (10.50) 0.3977 (10.00) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45
C12C c3163C8C10/97 printed in u.s.a.

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